The present invention relates to the manufacture of semiconductor integrated circuits. More particularly, the invention provides a technique including a method and apparatus for integrated circuit fabrication using an improved chemical-mechanical planarization or polishing (CMP) technique. But it will be recognized that the invention has a wider range of applicability; it can also be applied to the manufacture of flat panel displays, optical devices, electro-optical devices, and others.
In the manufacture of semiconductor integrated circuits, device geometries are becoming increasingly smaller. These smaller device geometries tend to cause a variety of problems during the manufacture of such circuits, especially for multi-metal layered devices. One of these problems is the contact via alignment between an upper conductive layer and a lower conductive layer. The contact alignment problem between these conductive layers is often caused by a non-uniform inter-dielectric layer therebetween. The non-uniform inter-dielectric layer is often characterized by peaks and valleys defined in the layer surface.
These peaks and valleys on the dielectric layer have also caused other limitations. In particular, an overlying metal layer would generally follow the topography of the underlying layer (i.e., dielectric layer), which is defined by peaks and valleys. Patterning this metal layer now having peaks and valleys is often difficult because of conventional lithography's depth-of-focus limitation. That is, different areas on the dielectric layer having different heights cause an overlying metal layer also having different heights, leading to improper focussing. Furthermore, even if the metal layer was deposited accurately overlying the dielectric layer, it would often be thinner at step edges, thereby leading to failure caused by problems such as thermal stress, metal fatigue, electro-migration, etc. Techniques have been proposed to reduce these layer non-uniformities.
One technique is the so-called photoresist etchback (REB) process. This photoresist etchback process uses the steps of applying a relatively non-viscous layer of photoresist overlying the surface having non-uniformities. The photoresist is developed leaving a relatively uniform layer of photoresist overlying the surface. An etching step removes horizontal portions of the photoresist and surface non-uniformities at about the same rate. Thus, the etching step reduces the height of peaks in the layer, thereby taking some of the non-uniformity out.
The REB process, however, has limitations. In fact, it consumes expensive fabrication chemicals such as photoresist and etchants, which add costs to the circuit. The process also uses valuable production time from both photoresist and etching equipment, which influences wafer turn-around-time. Photoresist also tends to introduce even more particulate contamination onto the circuits. Accordingly, the REB process has severe limitations in the manufacture of today's sub-micron sized devices.
Another technique is chemical-mechanical polishing or planarization, commonly termed CMP. CMP generally relies upon an apparatus 5 comprising a large rotating pad impregnated with an abrasive material, as illustrated by the simplified top-view diagram of FIG. 1. This apparatus includes a base plate 10. A circular rotating polishing pad 13 is mounted on the base 10. The pad 13 is rotated or spun by a driving motor (not shown), often located in the base 10. A chuck assembly 15 holds a semiconductor wafer 17, which is placed facedown on the rotating pad 13. As can be seen, the rotating pad has a diameter that is generally much larger than the diameter of the semiconductor wafer 17, thereby providing global planarization of the substrate.
A selected force is applied to the backside of the substrate to compress the face of the substrate against the rotating pad. The combination of the rotating pad, abrasive material, and selected force removes or polishes the surface non-uniformities from the face. The rotating pad has a diameter, often much larger than the diameter of the substrate. This large diameter pad can be quite effective in globally removing non-uniformities from surfaces of bulk materials, e.g., flat glass, semiconductor substrates, etc.
This large pad, however, often cannot remove local variations that may exist on a film (e.g., dielectric, metal, silicon, etc.) overlying the semiconductor wafer. As wafer sizes become larger (e.g., 8 inch, 12 inch, and greater), it is often difficult to remove the non-uniformities in the film overlying the wafer due to these local variations. The large pad also has local variations in itself, thereby causing further complications in processing the film on these wafers. These local variations on the pad can be spatial differences in pad thickness and spatial differences in the amount of abrasive materials. These variations of the abrasive material can lead to different chemical etching rates, which often cause even more processing complexities.
As device sizes become smaller, the large pad also can be a source for particulate contamination. Specifically, the large pad attracts particulate contamination from the environment and the wafer itself. The contamination accumulates on the pad, and can deposit onto the wafer, which may cause functional and reliability problems with the integrated circuits. The large pad also requires a massive machine, which occupies a large area of a fabrication plant, e.g. a large footprint. The large pad also rotates slowly and often cannot provide a great deal of pressure on the surface of today's larger semiconductor wafers (e.g., 6 inch, 8inch, 12 inch, etc.), thereby increasing process times. Accordingly, the conventional CMP technique has a variety of limitations in processing today's submicron sized devices.
From the above, it is seen that a technique for forming uniform layers of film materials during the manufacture of integrated circuits is often desirable.